This invention relates to application specific integrated circuit (“ASIC”) devices, and more particularly to the type of ASICs that are sometimes referred to as structured ASICs.
Structured ASICs are ASICs that, for any given product family, always have some of the same (or substantially the same) masks used in their fabrication. These masks that are always the same give all ASICs in the product family the same basic structure. Only some of the masks that are used to make particular ASICs in the family are modified or customized for that particular ASIC. This greatly simplifies the task of developing a particular ASIC, and it also greatly reduces the risk that the finished ASIC will not perform as expected.
An example of structured ASICs are those that are used to perform logic and other operations in a manner that is equivalent to a programmed field-programmable gate array (“FPGA”) integrated circuit. Chua et al. U.S. Pat. No. 7,243,329 shows examples of some aspects of structured ASICs of this kind.
FPGAs typically include many instances of programmable, general-purpose logic module circuitry. FPPAs also typically include instances of special-purpose circuitry such as blocks of memory (e.g., static random access memory or SRAM) circuitry, digital signal processing (“DSP”) circuitry, etc. Another typical feature of FPGAs is a network of programmable interconnection resources, whereby any of the other circuitry on the device can be interconnected in any of many different ways.
A structured ASIC product that may be designed for use in producing structured ASICs that are functionally equivalent to an FPGA product of the type described above (after the FPGA product has been programmed to implement a particular user's logic and other circuitry design) also typically includes many instances of (mask-programmable) general-purpose logic modules. Such a structured ASIC may also include instances of SRAM circuitry. The mask-programmable logic modules are typically used to perform the functions of the programmed logic modules in a functionally equivalent FPGA. The SRAM circuitry is typically used to perform the functions of the SRAM blocks in the functionally equivalent FPGA.
In situations of the type described above, an inefficiency can result in the design or architecture of the structured ASIC due to the fact that the structured ASIC architecture is typically given SRAM blocks similar in size and number to those in the architecture of the related FPGA. However, many user designs for the FPGA (and hence for a functionally equivalent structured ASIC) do not use all the SRAM resources thus provided. This can be due to the fact, for example, that logic and memory utilization rates differ across different user designs and applications. Some applications tend to be more logic intensive, while other applications tend to be more memory intensive. Because it is always difficult to strike an optimal balance point between how much logic and how much memory to include in the architecture of these devices, it would be desirable to provide a structured ASIC logic module flexible enough to perform either logic or memory functions.
One currently known structured ASIC architecture which is designed for use in providing ASICs that are functionally equivalent to programmed FPGAs has approximately 60% of its core area occupied by memory blocks. The remaining core area is occupied by general-purpose logic modules (used for logic and DSP functions). If a user does not use the above-mentioned embedded or dedicated memory in the user's design, a majority of the structured ASIC's core area is wasted. Nevertheless, the user is paying for this extra circuitry that was not used. In addition, leakage power due to the un-used memory blocks causes overall power consumption to increase. Another issue is that the large memory resources cause the general-purpose logic modules to be more spread apart. This tends to increase signal loading and reduces system performance. In some cases, this can also lead to routing congestion on the structured ASIC.